1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of forming a buried bit line.
2. Description of the Related Art
Dynamic random access memory (DRAM) is a type of volatile memory capable of storing a bit of data in each cell through the presence or absence of charges within its capacitor. Since charges stored within a DRAM cell may leak once power is off, data will be lost. In general, a DRAM cell consists of a metal-oxide-semiconductor (MOS) transistor and a capacitor.
FIGS. 1 through 4 are schematic cross-sectional views showing the progression of steps for producing a conventional DRAM unit. First, as shown in FIG. 1, a shallow trench isolation (STI) layer 102 is formed in a substrate 100. A plurality of bit lines 104 is formed over the substrate 100 and the STI layer 102. A plurality of source/drain regions 106 are formed in the substrate 100 between the word lines 104. Insulation material is deposited over the word lines 104 and into the space between the word lines to form an insulation layer 108.
As shown in FIG. 2, photolithographic and etching operations are carried out to form contact openings 110 in the insulation layer 108. The contact openings 110 expose a portion of the source/drain region 106. Conductive material is next deposited into the openings 110 and over the insulation layer 108 to form a conductive layer (not shown). The conductive layer is patterned to form contact pads 112. An insulation layer 114 is formed over the insulation layer 108 and the contact pads 112.
As shown in FIG. 3, photolithographic and etching operations are carried out to form a bit line opening 116 in the insulation layer 114. The bit line opening 116 exposes a portion of the contact pad 112. A bit line 118 that also fills the bit line opening 116 is formed over the bit line opening 116. Hence, the bit line 118 is electrically connected to the contact pad 112. An insulation layer 120 is formed over the insulation layer 114 and the bit line 118.
As shown in FIG. 4, node contact openings 122 are formed in the insulation layer 120. The node contact openings 122 expose a portion of the contact pad 112 not yet electrically connected to any bit line. A node contact 124 is formed inside each node contact opening 122. Capacitors (not shown) are subsequently formed above the substrate 100 to complete the fabrication of a DRAM cell.
In the aforementioned process, the node contact openings are formed after a structure of multiple conductve layers (including word lines and bit lines) isolated from each other by plurality of insulation layers is formed. Consequently, there is a considerable height difference between a peripheral circuit region and a device region in a silicon chip. This often leads to a subsequent planarization problem. Furthermore, as the level of device integration continues to increase, the node contact openings formed after the bit line have a bigger aspect ratio. With a big aspect ratio, node contact openings are more difficult to form, resulting in a node contact with low conductivity and a barrier layer with poor step coverage. Hence, electrical contact of the node contact is poor. To deal with these problems, manufacturers have to use expensive etching equipment and chemical deposition stations. However, this leads to an increase in the cost of production.